Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-03-26
1999-11-02
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
059789425
ABSTRACT:
A semiconductor tester high-speed system with Single Instruction-stream Multiple Data-stream (SIMD) organization, incorporating an event generator array, a plurality of pin channels for connecting to a device under test (DUT), a reconfigurable allocation switch for assignment of event generators to individual DUT pin channel connections, multi-clocking, and SIMD instruction cache. The result is a tester digital system exhibiting a maximum ratio of performance to hardware cost.
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Beausoliel, Jr. Robert W.
Iqbal Nadeem
Simd Solutions, Inc.
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