Start/stop circuit for performance counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S047300

Reexamination Certificate

active

11209215

ABSTRACT:
A circuit for tracking a number of clock cycles between occurrences of an event of interest. The circuit includes logic for asserting a run signal responsive to a first occurrence of the event of interest, logic for deasserting the run signal responsive to a second occurrence of the event of interest, and logic for incrementing a count value on each clock cycle while the run signal is asserted.

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