Static test sequence compaction using two-phase restoration and

Details Static test sequence compaction using two-phase restoration and Static test sequence compaction using two-phase restoration and

1998-08-18

1999-11-16

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714720, 714728, G01R 3128

Patent

active

059876360

ABSTRACT:
A technique for static compaction of test sequences is described. The method for static compaction according to the present invention includes two key features: (1) two-phase vector restoration, and (2) identification, pruning, and re-ordering of segments. Segments partition the compaction problem into sub-problems. Segments are identified, dynamically pruned and re-ordered to achieve further compaction and speed up.

REFERENCES:
patent: 5444717 (1995-08-01), Rotker et al.
Higami et al, "Static Test Compaction for IDDQ testing of Sequential Circuits", pp. 9-13, IEEE, Mar. 1998.
Guo et al, "on speeding-up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits", pp. 467-471, IEEE, Sep. 1998.
Pomeranz et al, "Static Compaction for Two-Pattern Test Sets", The Fourth Asian Test Symposium, IEEE 1995, pp. 222-228.
Srimat T. Chakradhar and Michael S. Hsiao, "Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits" Technical Report 1997, 97-C074-4-5506-5. Computers & Communications Research Lab, NEC USA Inc.
Surendra K. Bommu et al., "Static Test Sequence Compaction Based on Segment Reordering and Accelerated Vector Restoration," Technical Report 1998, 98-C014-4-5099-1. Computers and Communications Research Lab, NEC USA Inc.
Irith Pomeranz and Sudhakar M. Reedy, "Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits" Proceedings Int. Conf. on Computer Design pp. 360-365, 1997. University of Iowa, Aug. 1997.
Timothy J. Lambert and Kewal K. Saluja, "Methods for Dynamic Test Vector Compaction in Sequential Test Generation," in Proc. Int. Conf. on VLSI Design, pp. 166-169, Jan. 1996.
Irith Pomeranz and Sudhakar M. Reedy, "Dynamic Test Compaction for Syncronous Sequential Circuits using Static Compaction Techniques," in Proc. Fault-Tolerant Computing Symp., pp. 53-61, Jun. 1996.
Srimat T. Chakradhar and Anand Raghunathan, "Bottleneck Removal Algorithm for Dynamic Compaction in Sequential Circuits," IEEE Trans. on Computer-Aided Design, (Accepted for publication) 1997.
Michael S. Hsiao et al., "Sequential Circuit Test Generation Using Dynamic State Traversal," Proc. European Design and Test Conf., pp. 22-28, Feb. 1997.
Elizabeth M. Rudnick and Janak H. Patal, "Simulation-Based Techniques for Dynamic Test Sequence Compaction," Proc. Intl. Conf. Computer-Aided Design, pp. 67-73, Nov. 1996.

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