Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-02-24
2008-10-28
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000, C714S031000, C714S033000, C714S037000, C714S039000, C714S724000, C714S742000, C703S013000, C703S014000, C703S015000, C703S019000, C716S030000, C716S030000, C716S030000, C716S030000, C717S109000, C717S125000, C717S134000, C717S135000
Reexamination Certificate
active
07444574
ABSTRACT:
A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from multiple stimulation results. Each of these extracted building block events or “tags” are created from a slice of a graphical stimulation view, which slice is converted into a coded stimulus written in a high-level language code that represents the condition(s) that created the graphical simulation view. These coded stimuli (representing the tags) are stored in a library. To create a corner case scenario or sequence in the DUT, a user utilizes a graphical interface to select the different extracted tags from the library and combines them together.
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Davis Maureen Terese
Dunning Katherine Ann
Sawan Tony Emile
Dillon & Yudell LLP
International Business Machines - Corporation
Trimmings John P
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