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Flexible and extensible implementation of sharing test pins...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Flexible memory built-in-self-test (MBIST) method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flexible scan architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flexible test environment for automatic test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Flexible test environment for automatic test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flip flop circuit and apparatus using a flip flop circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flip flop circuit and apparatus using a flip flop circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flip flop circuit for scan test with two latch circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Flip-flop and scan path circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Flip-flop circuit for capturing input signals in priority order

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Flip-flop, shift register, and scan test circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Format control circuit and semiconductor test device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Full scan solution for latched-based design

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Full scan solution for latched-based design

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Fully X-tolerant, very high scan compression scan test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Functional block for integrated circuit, semiconductor...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Functional frequency testing of integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Functional frequency testing of integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Functional frequency testing of integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Functional pattern logic diagnostic method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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