Flip-flop and scan path circuit

Details Flip-flop and scan path circuit Flip-flop and scan path circuit

2006-04-04

2006-04-04

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07024605

ABSTRACT:
A scan path flip-flop so adapted that the value of the flip-flop will not be changed by set and reset signals at the time of a shift operation is provided. The scan path flip-flop includes a control terminal for receiving a control signal, which controls mode changeover between a scan path test mode and a normal operation mode; a set terminal for receiving a set signal; and a reset terminal for receiving a reset signal. A first OR gate is provided for inhibiting output of a signal at the set terminal and outputting a fixed value when the control signal is indicative of a scan path test. When the control signal is indicative of a scan path test, therefore, the flip-flop will not be set. A second OR gate is provided for inhibiting output of a signal at the reset terminal RESETB and outputting a fixed value when the control signal is indicative of the scan path test. When the control signal indicates the scan path test, therefore, the flip-flop will not be reset.

REFERENCES:
patent: 6393592 (2002-05-01), Peeters et al.
patent: 62-239071 (1987-10-01), None
patent: H04-72583 (1992-03-01), None
patent: H07-35823 (1995-02-01), None
patent: 7-306244 (1995-11-01), None
patent: H11-85562 (1999-03-01), None
patent: 2000-2754 (2000-01-01), None
patent: 2001-196539 (2001-07-01), None

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