Flexible and extensible implementation of sharing test pins...

Details Flexible and extensible implementation of sharing test pins... Flexible and extensible implementation of sharing test pins...

2006-05-16

2006-05-16

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S027000

Reexamination Certificate

active

07047470

ABSTRACT:
A library to be used in an ASIC design system includes information to be used for verification of test structures. The library includes information regarding the ability to combine test pins for verification of the test structure and information regarding the sharing of ports for verification of the test structure. A user of the ASIC design system can include custom test structures in the library for verification.

REFERENCES:
patent: 6499125 (2002-12-01), Ohta et al.
patent: 6557153 (2003-04-01), Dahl et al.
patent: 6564363 (2003-05-01), Dahl et al.
patent: 6678875 (2004-01-01), Pajak et al.
patent: 6836872 (2004-12-01), Abdennadher

Affiliated with

Also associated with

Rating

Flexible and extensible implementation of sharing test pins... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flexible and extensible implementation of sharing test pins..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flexible and extensible implementation of sharing test pins... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3632063