Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-20
2004-03-16
Decady, Albert (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06708301
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a functional block for integrated circuit (hereinafter, simply referred to as an “IC functional block”) implemented as a macro cell including a self-diagnosis circuit for detecting a fault between functional blocks, for example. The present invention also relates to a semiconductor integrated circuit that has been designed using the IC functional block and to respective methods for testing and designing the semiconductor integrated circuit.
BACKGROUND ART
In recent years, demand for designing a semiconductor integrated circuit more efficiently by implementing the circuit as a combination of functional blocks such as macro cells has been increasing. If a semiconductor integrated circuit is designed by combining a plurality of functional blocks with each other, however, there arises a problem in how to test a signal line interconnecting these functional blocks together. To solve this problem, according to a conventional technique, the operations of a pair of functional blocks interconnected are tested by externally supplying test data for operating these functional blocks. According to another conventional technique, scan circuits are provided for an output section of a functional block on the transmitting end and for an input section of an associated functional block on the receiving end, respectively. And the functional block on the transmitting end is tested through a scanning operation.
Hereinafter, a conventional method for testing a semiconductor integrated circuit made up of a plurality of functional blocks will be described with reference to the drawings.
FIG. 25
illustrates a simplified block configuration for a semiconductor integrated circuit to exemplify a method for testing the semiconductor integrated circuit as a first prior art example. As shown in
FIG. 25
, the semiconductor integrated circuit
500
includes first and second functional blocks
501
and
502
, for example. A plurality of inter-block signal lines
503
are provided between the first and second functional blocks
501
and
502
. External input terminals
504
, through which parallel data can be input, are provided for the input end of the first functional block
501
. External output terminals
505
, through which parallel data can be output, are provided for the output end of the second functional block
502
.
A test is carried out between these functional blocks in the following manner. First, a test data pattern is input through the external input terminals
504
. The first functional block
501
supplies a result of an operation, which has been performed responsive to the test data pattern received, as an output signal onto the inter-block signal lines
503
. Next, an output signal, which might have been affected by a fault during the propagation through the inter-block signal lines
503
, is input to the second functional block
502
. The second functional block
502
outputs a result of an operation, which has been performed responsive to the input signal, through the external output terminals
505
. Based on this result of operation, it is determined whether or not there is any fault, thereby testing the semiconductor integrated circuit
500
. A similar technique is also applicable to even a semiconductor integrated circuit including a multiplicity of functional blocks. That is to say, a test data pattern is input to each of these functional blocks, and it is decided whether the output result thereof is correct or erroneous.
FIG. 26
illustrates a simplified block configuration for a semiconductor integrated circuit to exemplify another method for testing the semiconductor integrated circuit as a second prior art example. As shown in
FIG. 26
, the semiconductor integrated circuit
510
includes first and second functional blocks
511
and
512
, for example. A plurality of interblock signal lines
513
are provided between the first and second functional blocks
511
and
512
. A scan-in pin
514
, through which scan data is input, is provided for the input end of the first functional block
511
. A scan-out pin
515
, through which the scan data is output, is provided for the output end of the second functional block
512
. At the output end of the first functional block
511
, a shift register
516
, which can output data in parallel to the outside, is provided. At the input end of the second functional block
512
, a shift register
517
, which can receive data in parallel from the outside, is provided. In this example, the scan-in pin
514
, shift registers
516
and
517
and scan-out pin
515
are connected in series to each other.
A testing method is performed in the following manner. First, a test data pattern is scanned in through the scan-in pin
514
while being shifted by the shift register
516
. The first functional block
511
supplies a result of an operation, which has been performed responsive to the test data pattern received, as an output signal onto the inter-block signal lines
513
. Next, an output signal, which might have been affected by a fault during the propagation through the interblock signal lines
513
, is input to the shift register
517
of the second functional block
512
. The second functional block
512
shifts out the received signal through the scan-out pin
515
. Based on the resultant data, it is determined whether or not there is any fault, thereby testing the semiconductor integrated circuit
510
.
In the semiconductor integrated circuit and the testing method thereof according to the first prior art example, a plurality of pre-designed functional blocks (e.g., macro cells) are combined and reused to increase the efficiency in designing. However, if the first and second functional blocks
501
and
502
are combined and reused, it might be difficult for the user to produce test data patterns that should be propagated through the respective functional blocks. This is because the user is not acquainted with the internal configurations and operations of the functional blocks. Also, if the circuit sizes of the first and second functional blocks
501
and
502
are huge, then it is extremely complicated and very difficult to produce test data patterns that should be propagated through the respective functional blocks.
Also, the semiconductor integrated circuit and the testing method thereof according to the second prior art example require a shift operation to propagate the test data patterns through respective functional blocks. Thus, a large number of clock cycles should be consumed for that purpose, and it is difficult to supply the test data patterns rapidly and continuously enough to detect a fault promptly.
In view of the foregoing respects, a first object of the present invention is to make a test easily executable among functional blocks even if the user does not know much about the internal configurations and operations of the functional blocks combined or if the circuit sizes of the functional blocks are enormous. A second object of the present invention is to make the signal propagation delay fault between the functional blocks readily testable.
DISCLOSURE OF INVENTION
A first IC functional block according to the present invention achieves the first object and includes a test data output circuit for outputting test data responsive to a control signal indicating a test data transmission state.
According to the first IC functional block, a test data output circuit for outputting test data is provided within the IC functional block. Thus, if a semiconductor integrated circuit is constructed of the block and another IC functional block including a circuit that can receive the test data and compare it to an expected value, then the test data can be transmitted and received even when the user does not know much about the internal configuration and operation of the IC functional blocks. Accordingly, even if IC functional blocks are combined or the circuit sizes of the IC functional blocks are huge, a test among the IC functional blocks can be carried out easily and accurately in the semiconductor
Hiraoka Toshihiro
Ohta Mitsuyasu
Takeoka Sadami
Britt Cynthia
De'cady Albert
Matsushita Electric - Industrial Co., Ltd.
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