Full scan solution for latched-based design

Details Full scan solution for latched-based design Full scan solution for latched-based design

2007-06-15

2009-06-02

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07543207

ABSTRACT:
A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the normal mode, the device operates as a transparent latch, passing a data input to its output. When in test mode, the device is operable to pass scan data down a scan chain and to inject scan data into the data path.

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