Flip flop circuit and apparatus using a flip flop circuit

Details Flip flop circuit and apparatus using a flip flop circuit Flip flop circuit and apparatus using a flip flop circuit

2008-04-01

2008-04-01

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

11099696

ABSTRACT:
A flip flop circuit includes a first latch circuit which latches an input data at a leading edge of a clock signal, a second latch circuit which latches the input data at a trailing edge of the clock signal, and a selector which, during a period from the leading edge to the trailing edge of the clock signal, selects an output data from the first latch circuit, and during a period of the trailing edge to a next leading edge of the clock signal, selects an output data from the second latch circuit, in which one of the first latch circuit and the second latch circuit functions as a master latch circuit for receiving a scan data during a scan mode, and the other of the first latch circuit and the second latch circuit functions as a slave latch circuit for latching data outputted from the master latch circuit.

REFERENCES:
patent: 6181179 (2001-01-01), Kanba
patent: 6300809 (2001-10-01), Gregor et al.
patent: 6525565 (2003-02-01), Young et al.
patent: 7132854 (2006-11-01), Chen et al.
patent: 2002/0175704 (2002-11-01), Young et al.
patent: 2003/0218488 (2003-11-01), Parulkar et al.
patent: 102 19 119 (2003-11-01), None
patent: 05-075401 (1993-03-01), None
patent: 05-267998 (1993-10-01), None
patent: 06-160477 (1994-06-01), None
patent: 07-095013 (1995-04-01), None
Notice of First Office Action dated Jul. 27, 2007 in Chinese Application No. 2005100648477 and English Translation thereof.
Japanese Office Action dtd Oct. 23, 2007 for JP Patent Application No. 2004-113439.

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