Format control circuit and semiconductor test device

Details Format control circuit and semiconductor test device Format control circuit and semiconductor test device

2007-05-08

2007-05-08

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10952678

ABSTRACT:
There is provided a semiconductor test apparatus which assuredly detects an inhibited edge only which affects a test pattern and truly requires an error warning. This semiconductor test apparatus includes: a real time selector which receives a plurality of sets of waveform data, receives a plurality of sets of timing data, selects and outputs predetermined waveform data and timing data, inhibits a next edge immediately following the current edge and outputs an inhibiting signal when an edge with the same polarity which is continuous in an interval shorter than a proximity limit time exists in the waveform data; and a detector which receives the waveform data, the timing data and the open signal, and outputs fail signal when an edge with a polarity reverse to that of an inhibited edge exists in the proximity limit time before the inhibited edge.

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Teruo Tamama et al. “Key Technologies for 500-MHz VLSI Test System “Ultimate””, NTT LSI Laboratories, Sep. 12, 1988.

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