Flip flop circuit for scan test with two latch circuits

Details Flip flop circuit for scan test with two latch circuits Flip flop circuit for scan test with two latch circuits

1998-02-26

1999-12-21

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714729, G06F 1106

Patent

active

060063483

ABSTRACT:
A flip flop circuit for a scan test comprises a first latch circuit for latching and outputting data signal D in synchronization with control signal CLK when control signal SC1 is set at one level and latching and outputting scan in data signal SIN in synchronization with control signal SC1 when control signal CLK is set at the other level, and a second latch circuit for latching and outputting an output of the first latch circuit in synchronization with control signal CLK when control signal SC2 is set at one level and latching and outputting an output of the first latch circuit in synchronization with control signal SC2 when control signal CLK is set at the other level. In this way, the area of the circuit is decreased by commonly using one latch circuit for a data signal and a scan in data signal. Also, the skew adjustment is not required during a scan test by operating with two-phase clocks during both scan shift operation and scan normal operation.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 5175447 (1992-12-01), Kawasaki et al.
patent: 5527223 (1996-06-01), Dervisoglu
patent: 5598120 (1997-01-01), Yurash
patent: 5838693 (1998-11-01), Morley

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