Flexible memory built-in-self-test (MBIST) method and apparatus

Details Flexible memory built-in-self-test (MBIST) method and apparatus Flexible memory built-in-self-test (MBIST) method and apparatus

2005-11-18

2008-10-07

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

07434131

ABSTRACT:
Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.

REFERENCES:
patent: 5253349 (1993-10-01), Kreitzer
patent: 5469443 (1995-11-01), Saxena
patent: 5661732 (1997-08-01), Lo et al.
patent: 6070252 (2000-05-01), Xu et al.
patent: 6347056 (2002-02-01), Ledford et al.
patent: 6415403 (2002-07-01), Huang et al.
patent: 6553527 (2003-04-01), Shephard
patent: 6567942 (2003-05-01), Shepard, III
patent: 6651201 (2003-11-01), Adams et al.
patent: 6658611 (2003-12-01), Jun
patent: 6671837 (2003-12-01), Reohr, Jr. et al.
patent: 6671843 (2003-12-01), Kebichi et al.
patent: 6760872 (2004-07-01), Gupta et al.
patent: 6769081 (2004-07-01), Parulkar
patent: 6801461 (2004-10-01), Hii et al.
patent: 6834361 (2004-12-01), Abbott
patent: 6874111 (2005-03-01), Adams
patent: 6950974 (2005-09-01), Wohl et al.
patent: 7168005 (2007-01-01), Adams et al.
patent: 7181659 (2007-02-01), Bravo et al.
patent: 7206979 (2007-04-01), Zarrineh et al.
patent: 7216198 (2007-05-01), Ito et al.
patent: 2003/0167431 (2003-09-01), Nicolaidis et al.
patent: 2004/0123200 (2004-06-01), Caty et al.
patent: 2004/0153885 (2004-08-01), Chauvel et al.
patent: 2004/0158786 (2004-08-01), Caty et al.
patent: 2004/0230395 (2004-11-01), Basto
patent: 2005/0120270 (2005-06-01), Anand et al.
patent: 2005/0172180 (2005-08-01), Damodaran et al.
patent: 2005/0204231 (2005-09-01), Mukherjee et al.
patent: 0 472 818 (1992-03-01), None
patent: 1 388 788 (2004-02-01), None
patent: WO 02/089146 (2002-11-01), None
Zarrineh et al., “Programmable Memory BIST and a New Synthesis Framework”, 1999.
Huang et al., “A Programmable BIST Core for Embedded DRAM”, IEEE, Jan.-Mar. 1999, pp. 59-70.
Zarrineh et al., “On Programmable Memory Built-In Self Test Architectures”, 1999.
Appello et al., “Exploiting Programmable BIST for the Diagnosis of Embedded Memory Cores”, IEEE, 2003, pp. 379-385.
Jakobsen et al., “Embedded DRAM Built In Self Test and Methodology for Test Insertion,” IEEE 2001, paper 35.1, pp. 975-984.
U.S. Appl. No. 11/283,527, filed Nov. 18, 2005, Mukherjee et al.
U.S. Appl. No. 11/283,499, filed Nov. 18, 2005, Mukherjee et al.
International Search Report for International Application No. PCT/US05/42029, mailed Jun. 8, 2006.
Chen and Dey, “DEFUSE: A Deterministic Functional Self-Test Methodology for Processors,”Proc. IEEE VLSI Test Symposium, pp. 255-262, 2000.
Cheng, “Comprehensive Study on Designing Memory BIST: Algorithms, Implementations and Trade-offs,”EECS 579, University of Michigan, Dec. 16, 2002.
Jervan et al., “A Hybrid BIST Architecture and its Optimization for SoC Testing,”In International Symposium on Quality Electronic Design, pp. 273-279, 2002.
Touba, “Circular BIST with State Skipping,”IEEE Transactions on Very Large Scale Integration(VLSI)Systems10(5):668-672, Oct. 2002.
Könemann, “A Pattern Skipping Method for Weighted Random Pattern Testing,”European Test Conference 1993, Proceedings of ETC 93, Third, pp. 418-425, Apr. 19-22, 1993.
Office Action dated Mar. 27, 2007, issued in U.S. Appl. No. 11/283,499, filed Nov. 18, 2005.
Office Action dated Oct. 2, 2007, issued in U.S. Appl. No. 11/283,527, filed Nov. 18, 2005.
Office Action dated Oct. 19, 2007, issued in U.S. Appl. No. 11/283,499, filed Nov. 18, 2005.
TechTarget website, “Plan for the Worst, Get the Best Results,” Recent Vendor Reports on Circuit Design, downloaded Nov. 26, 2007 from http://www.bitpip.com/tlist/Circuit-Design.html, Podcast sponsored by iPass, Inc., orginally posted Dec. 12, 2006.
European Search Report dated Mar. 19, 2008, European Patent Application EP 05 84 9415, Publication Date Aug. 29, 2007.
Communication Pursuant to Article 94(3) EPC, dated Jun. 9, 2008, from European Patent Office in European Patent Application No. 05849415.4.

Affiliated with

Also associated with

Rating

Flexible memory built-in-self-test (MBIST) method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flexible memory built-in-self-test (MBIST) method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flexible memory built-in-self-test (MBIST) method and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4017343