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Dynamic scan circuitry for A-phase

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Dynamic verification traversal strategies

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable precision signal delay test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable precision signal delay test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Easy to program automatic test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Edge-triggered master + LSSD slave binary latch

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Edge-triggered scan flip-flop and one-pass scan synthesis...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Efficient built-in self test for embedded memories with differin

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Efficient compression and application of deterministic...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Efficient on-pitch scannable sense amplifier

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Efficient scan chain insertion using broadcast scan for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Efficient word recognizer for a logic analyzer

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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eFuse programming data alignment verification apparatus and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Electrical circuit and method for testing a circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Electrical circuit unit and a method for testing the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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