Dynamically reconfigurable shared scan-in test architecture

Details Dynamically reconfigurable shared scan-in test architecture Dynamically reconfigurable shared scan-in test architecture

2004-05-28

2008-08-26

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S037000

Reexamination Certificate

active

07418640

ABSTRACT:
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

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