Edge-triggered master + LSSD slave binary latch

Details Edge-triggered master + LSSD slave binary latch Edge-triggered master + LSSD slave binary latch

2004-11-30

2008-07-15

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000, C327S202000

Reexamination Certificate

active

07401278

ABSTRACT:
A binary latch that operates as an edge-triggered flip-flop and which is LSSD-testable that comprises an edge triggered master. The binary latch comprises an edge triggered master flip-flop (2), with a clock input connected to the system clock (SYS_CLK), with a data input (DI) and with an output (DO), a level sensitive scan design (LSSD) slave latch (3), connected to the output (DO) of the master flip-flop (2), a NAND gate (4) with a first input (41) connected to the system clock (SYS_CLK), a second input (42) connected to a test input (TEST) and with an output (43) connected to the LSSD slave latch clock input (LSSD_clk).

REFERENCES:
patent: 5838693 (1998-11-01), Morley
patent: 5920575 (1999-07-01), Gregor et al.
patent: 6271700 (2001-08-01), Itaya
patent: 7038494 (2006-05-01), Morton
patent: 7039843 (2006-05-01), Zhang

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