Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-02
2002-05-14
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C327S202000
Reexamination Certificate
active
06389566
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to the design of digital integrated circuits, and more specifically to an improved edge-triggered scan flip-flop and one-pass scan synthesis method.
The use of integrated circuits is widespread and pervasive. Integrated circuits implement complex logic operations, and often do so through the use of an exceedingly large number of logic gates. A significant concern in the design and testing of integrated circuits is that the integrated circuit, often comprising well over one million logic gates, implements specified logic operations without error.
Ideally, every possible combination of inputs to an integrated circuit is applied when the integrated circuit is in every possible internal logic state, thus allowing every possible output of the circuit to be compared with the functional requirements of the circuit. However, even for a combinational circuit, which is a circuit in which the outputs of the circuit depend directly on the inputs to the circuit, and which thereby does not contain memory elements, the number of possible input combinations is sufficiently large that the test of the circuit becomes an NP hard problem, that is one that cannot be solved in polynomial time. For a sequential circuit, which is a circuit that contains internal memory and thus may have a number of internal logic states, the problem of testing every conceivable input combination in every combination of logic states of the circuit becomes even more intractable.
Further, testing of the circuit by manipulating the primary inputs and examining the primary outputs provides little information as to a location of a fault within the circuit. The knowledge that a certain combination of inputs to a circuit results in an incorrect combination of outputs from the circuit may be of little use in determining where in the circuit the error occurs.
One method known in the art of providing additional detail as to the internal operation of the circuit is to replace flip-flops normally found in the circuit with scan flip-flops. Generally speaking, almost any flip-flop present in a circuit may be converted to a scan flip-flop. Often a non-scan flip-flop is made scannable by adding a scan data input which is passed to a flip-flop output through the use of either a multiplexer and associated control signal or an independent clock. Such modifications increase circuit area and power requirements, and may otherwise affect circuit operation.
A scan flip-flop may be used as a control point for inserting a value into a circuit, or as an observation point for observing a value at a point in the circuit. Scan flip-flops are generally tied, or stitched, together to form a scan chain, with the scan chain forming a serial shift register. Data may be shifted in to provide input values for the circuit, or shifted out to capture the state of a portion of the circuit.
FIG. 1
illustrates a digital logic circuit. The digital logic circuit includes combinational circuit elements
11
,
13
. Scan flip-flops
15
A-G are dispersed about the combinational circuit elements
11
,
13
. Each of the scan flip-flops
15
A-G has four input ports for receiving associated input signals and one output port for outputting an associated output signal. The input ports are a data-in input port (D
IN
), a scan-in input port (S
IN
), a clock input port (CLK), and a test mode signal input port ({overscore (N)}/T). Each of the scan flip-flops has a single data-out output port (Q). The output Q is set to D
IN
after the rising edge of the clock signal when the test mode signal is set to a {overscore (TEST)} value. Thus, when the test mode signal is set to {overscore (TEST)} the scan flip-flop acts as an edge-triggered flip-flop. When the test mode signal is set to {overscore (TEST)}, however, the output signal Q is set to S
IN
after the rising edge of the clock signal. Thus, the scan flip-flops are edge-triggered flip-flops made scannable by adding a scan input and a multiplexer with an associated control signal.
In the digital logic circuit of
FIG. 1
, the combinational circuit
11
has at least four outputs
17
A-D, each of which is passed to the D
IN
ports of the scan flip-flops
15
A-D, respectively. The combinational circuit
13
has at least four inputs
19
A-D, which are provided by the Q data output ports of the scan flip-flops
15
A-D, respectively. The combinational circuit
13
also has at least three outputs
17
E-G, which are connected to the D
IN
ports of the flip-flops
15
E-G, respectively. All of the scan flip-flops
15
A-G are provided a common clock CLK signal
21
and a common test mode {overscore (N)}/T signal
23
.
The scan flip-flops
15
A-G are formed into a serial scan chain, i.e., a serial shift register, by connecting the Q data output of one scan flip-flop to the S
IN
port of another scan flip-flop. Accordingly, in addition to connecting the Q data output
19
A of scan flip-flop
15
A to the combinational circuit
13
, the Q data output
19
A is also connected to the S
IN
scan input port of scan flip-flop
15
B. Similarly, the Q data output
19
B is connected to the S
IN
input port of scan flip-flop
15
C, the Q data output
19
C is connected to the S
IN
input port of scan flip-flop
15
D, the Q data output
19
D is connected to the S
IN
input port of scan flip-flop
15
E, the Q data output
19
E is connected to the S
IN
input port of scan flip-flop
15
F, and the Q data output
19
E is connected to the S
IN
input port of scan flip-flop
15
G. In the circuit of
FIG. 1
, the S
IN
input
20
to scan flip-flop
15
A is accessible by a circuit tester, and the Q data output
19
G of scan flip-flop
15
G is readable by the circuit tester. Accordingly, the scannable flip-flops
15
A-G are stitched together to form a serial chain in the order of
15
A-
15
B-
15
C-
15
D-
15
E-
15
F-
15
G.
The scan flip-flops act both as control points and observation points. Control points, of course, may be treated as pseudo-primary inputs (PIs) and observation points may be treated as pseudo-primary outputs (POs). By way of example, for the circuit of
FIG. 1
the scan flip-flops
15
A-G are first treated as pseudo-PIs and are provided an input test vector comprised of state bits. The input test vector is provided by setting the test mode signal to {overscore (TEST)} and sequentially placing input data on the S
IN
line
20
every clock cycle. The first clock cycle after the input data is placed on the S
IN
line shifts the input data to the S
IN
input of the next scan flip-flop in the scan chain. Accordingly, by sequentially placing data on the scan in line
20
on sequential clock cycles, each of the scan flip-flops in the scan chain may be loaded with a state bit from the test vector. Thereafter setting the test mode signal to {overscore (TEST)} allows for normal circuit operation, with the circuit utilizing the data input to the scan flip-flops as pseudo-primary outputs. After providing the circuit one or more (usually one) clock pulses to drive the system to an expected desired state the test mode signal is again set to {overscore (TEST)}. Thereafter providing clock signals to the circuit causes the data present on the output ports of the scan flip-flops to be sequentially shifted to the next scan flip-flop in the scan chain, with the data being read from output
19
G by a tester.
Proper operation of the scan chain therefore generally requires that the scan shift chain operate in a race-free manner. If a race condition exists then the data in the scan chain may be corrupted and provide either an incorrect test vector or an incorrect indication of system state. For example, during a scan data shift operation an edge of the clock signal may reach scan flip-flop
15
D a period of time prior to the edge of the clock signal reaching scan flip-flop
15
E. If the period of time is sufficiently long, the input to the scan flip-flop
15
D may be passed through the scan flip-flop
15
D and propagated to the scan flip-flop
15
E before the data previously at the input to scan flip-flop
Amerian Mehran
Iyengar Srinivasan R.
Wagner Kenneth D.
Christie Parker & Hale LLP
De'cady Albert
Lamarre Guy J.
S3 Incorporated
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