Dynamic scan circuitry for A-phase

Details Dynamic scan circuitry for A-phase Dynamic scan circuitry for A-phase

2005-09-27

2005-09-27

DeCady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

06950973

ABSTRACT:
A first dynamic logic circuit has an output node on which a scan value is provided during scan, a second dynamic logic circuit, and one or more third dynamic logic circuits. The first dynamic logic circuit and the second dynamic logic circuit are in a first dynamic phase during functional operation. The third dynamic logic circuits are in a second dynamic phase during functional operation, and an output of the third dynamic circuits is sampled in response to the scan value during scan. In one embodiment, a first clock controls evaluation of the second dynamic logic circuit, and the second clock controls evaluation of the third dynamic logic circuits. The clocks may be generated responsive to a scan clock and/or a scan mode signal to generate at least one evaluate pulse on the first clock and the second clock prior to sampling the output of the third dynamic circuits.

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