Timing generator for testing semiconductor storage devices
Timing-aware test generation and fault simulation
Tool to reconfigure pin connections between a DUT and a tester
Tool to reconfigure pin connections between a DUT and a tester
Total configuration memory cell validation built in self...
Trading propensity-based clustering of circuit elements in a...
Trading propensity-based clustering of circuit elements in a...
Transient analysis device for analog/digital mixed circuit...
Transmission device, reception device, test circuit, and...
Transparently gathering a chips multiple internal states via...
Tristate buses
Two boundary scan cell switches controlling input to output...
Two pass multi-state parallel test for semiconductor device
Uniform testing of tristate nets in logic BIST
Universal method and apparatus for controlling a functional...
Use of a scan chain for configuration of BIST unit operation
User available body scan chain
Using clock gating or signal gating to partition a device...
Using statistical signatures for testing high-speed circuits
Utilizing multiple bitstreams to avoid localized defects in...