Total configuration memory cell validation built in self...

Details Total configuration memory cell validation built in self... Total configuration memory cell validation built in self...

2005-07-20

2008-08-05

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C326S039000, C365S201000

Reexamination Certificate

active

07409610

ABSTRACT:
A built in self test (BIST) circuit is provided for a programmable logic device (PLD) constructed from fixed or hard core logic that includes circuitry to write recurring patterns of bits in the configuration memory in a frame by frame manner and read the cell state to enable the validation of every configuration bit at power up. The BIST circuitry can further be used to program the recurring patterns into the configuration memory, and then read frames of the configuration memory to detect the occurrence of single event upsets (SEU) that corrupt data in the configuration memory. The recurring patterns programmed do not require time consuming functional configuration of the PLD, and can be done in a production environment after power up without knowledge of how the PLD will later be configured. No soft logic is needed to form the BIST circuit, enabling 100% test coverage of the programmable configuration memory cells.

REFERENCES:
patent: 6839873 (2005-01-01), Moore
patent: 6874110 (2005-03-01), Camarota
patent: 6968487 (2005-11-01), Bryant et al.
patent: 7167404 (2007-01-01), Pathak et al.
Gericota et al., On-line Testing of FPGA Logic Blocks Using Active Replication, 2000, IEEE, pp. 1-12.
Tahoori et al., Automatic Configuration Generation for FPGA Interconnect Testing, 2003, IEEE, pp. 1-6.

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