Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-10-06
2003-04-15
Kim, Kenneth S. (Department: 2783)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
72
Reexamination Certificate
active
06550031
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The apparatus and method according to the invention pertains to miscellaneous logic embedded in a microcontrollers, and more specifically, using computer software and scan hardware to capture data from the miscellaneous logic.
2. Description of the Related Art
The proliferation of electronic goods such as telephones, televisions, and video camcorders has been made possible by integrated circuit technology. One type of integrated circuit especially important to electronic devices is the microcontroller.
A microcontroller, or embedded controller, is similar to a microprocessor as used in a personal computer, but with a great deal of additional functionality combined onto the same monolithic semiconductor substrate (i.e., chip). In a typical personal computer, the microprocessor performs the basic computing functions, but other integrated circuits perform functions such as communicating over a network, providing input/output with the user, and controlling peripherals.
In a typical microcontroller, many of these functions are embedded within the integrated circuit chip itself A typical microcontroller, such as the Am186ES by Advanced Micro Devices, Inc., of Sunnyvale, Calif., not only includes a core microprocessor, but further includes a memory controller, a direct memory access (DMA) controller, an interrupt controller, and both asynchronous and synchronous serial interfaces. In computer systems, these peripheral devices are typically implemented as separate integrated circuits, requiring a larger area and increasing the size of the product. By embedding these functions within a single chip, size and cost are reduced, often important in consumer products.
From a consumer products designer's viewpoint, often the particular combination of added features make a particular microcontroller attractive for a given application. Many microcontrollers are available that use the standard 80×86 microprocessor instructions, allowing for software to be easily developed for such microcontrollers. Because of the similar execution unit instruction sets, the added features often become principal differentiating criteria between particular microcontrollers.
The miscellaneous logic embedded in a microcontroller can be input/outputs of combinational logic, memory devices such as latches, or registers of a peripheral device embedded in the microcontroller. Typical peripheral device registers include state registers, instruction registers, address registers, status registers and data registers. Depending on the peripheral, certain registers store configuration information needed for the peripheral's proper operation during start up. On system start up, the execution unit initializes each peripheral device with device specific initial configurationdata. This initialization could occur during a cold start-up, zero-volt suspend/resume procedure or after a system crash.
In addition to having peripheral devices, many of today's microcontrollers have embedded test circuitry. In 1985, a group of European companies formed Joint European Test Action Group (JETAG) to devise ways to reduce manufacturing costs. One concept was to incorporate such test circuitry into standard components (controlled via software), eliminating the need for sophisticated in-circuit test equipment. This concept gained support in the U.S., where in 1988, several North American companies formed the Joint Test Access Group (JTAG) consortium to formalize the concept. In 1990, the Institute of Electrical and Electronic Engineers (IEEE) refined the concept and created the 1149.1 standard (which is incorporated herein by reference), known as IEEE Standard Test Access Port and Boundary Scan Architecture. In addition to microcontrollers, JTAG circuitry can be incorporated into microprocessors, applications specific integrated circuits (ASICs), or any other discrete device that conforms to the IEEE 1149.1 specification.
In the JTAG architecture, a JTAG test device is connected to a microcontroller and performs a “boundary-scan test” on the microcontroller. Boundary scan cells contain shift register elements that connect together to form a scan path around the core logic circuit. Input/Output (I/O) signals freely pass between integrated circuit (IC) pins and the core logic, through the boundary scan cells, in normal mode. However, in test mode, only test signals are allowed to pass into or out of the core logic, via a test port and through the boundary scan chain, providing observability and controllability of the input and output signals. The JTAG test commands are typically drawn from a fairly limited set of commands particularly adapted for testing the interconnections of microcontrollers and are not typically well suited for testing or monitoring its internal logic. Instructions and associated data for testing are read serially into each microcontroller peripheral boundary scan cell registers and read out serially, and after the instructions has been carried out the result is read out serially.
Also, access to miscellaneous logic of the microcontroller may not be possible using processor I/O commands. Some of miscellaneous logic may not have both read/write capabilities. Thus, data cannot be written to miscellaneous logic such as read-only registers with processor I/O commands and data cannot be read from miscellaneous logic such as write-only registers with processor I/O commands.
In addition, traditional scan techniques required a system to halt so that scan data could be shifted into the scan path. This technique for scanning out data would generally be unacceptable for real-time systems. Furthermore, for capturing scan data for miscellaneous logic the microcontrollers would generally need to be halted so that the miscellaneous logic can output their data onto the scan path. Thus, capturing data can possibly reduce device throughput.
SUMMARY OF THE INVENTION
According to the present invention, a scan path is used to capture data of miscellaneous logic embedded in a microcontroller, such as input/outputs of combinational logic, memory devices such as latches, peripherals in a microcontroller, or a discrete device incorporating scan hardware. The data is captured in scan cells, such as latches or flip-flops, but the scan cells are implemented in multiple stages. There can be up to N stages of scan cells, where N is greater than 1. Each miscellaneous logic is coupled to a corresponding scan cell of a 1st stage; each 1st state scan cell is coupled to a corresponding 2nd stage state scan cell, and so on. These additional stages of scan cells allow multiple “snapshots” of the scanned logic to be taken without first scanning previous “snapshots”. Each stage of state scan cells can store input/output data of the miscellaneous logic and can eventually be scanned out. At least the Nth stage of scan cells are serially coupled together to form a scan path. Should the miscellaneous logic be peripherals embedded in the microcontroller, the scan paths of each peripheral are preferably serially coupled together. If desired, the scanned information can be used for diagnostics, among other things.
The capturing of data can occur while the microcontroller is running other applications. It is unnecessary to halt the microcontroller to capture the data. In addition, the use of multiple stages of scan cells allows the storage of the data should it be impossible to scan the data out as quickly as it is captured.
A trigger can be used to capture the data of the miscellaneous logic into scan cells. When the scan cells are triggered, the data in the miscellaneous logic are loaded into the 1st stage of state scan cells. In addition, the states in the 1st stage of scan cells are loaded into the 2nd stage, and so on, up to the Nth stage of scan cells. The trigger can be initiated under certain criteria. The criteria can be activation of the trigger by an operator, the happening of an event, the lapse of a predetermined time period, or on other conditions.
REFERENCES:
patent: 5598421 (1997-0
Godfrey Gary M.
Goodrich, III Floyd
Advanced Micro Devices , Inc.
Akin Gump Strauss Hauer & Feld & LLP
Kim Kenneth S.
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