Two pass multi-state parallel test for semiconductor device

Details Two pass multi-state parallel test for semiconductor device Two pass multi-state parallel test for semiconductor device

1999-08-12

2002-06-18

Chung, Phung M. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C365S201000

Reexamination Certificate

active

06408411

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to test circuits for semiconductor devices, and more particularly to circuits that provide internal test results data on the output pins of a semiconductor device.
BACKGROUND OF THE INVENTION
Semiconductor memory devices typically include one or more memory arrays, each of which includes a large number of memory cells. In a standard mode, in response to an applied address, selected memory cells are accessed and given operation is allowed to take place (e.g., a read, write, program or erase operation). The memory cells are usually logically arranged into input/output (I/O) groups in such a way that an applied address will access a memory cell from each I/O group. For example, a memory device may include 128 I/O groups, thus, the applied address would access one memory cell from each of 128 I/O groups. Selected of the 128 memory cells can then be selected depending upon the data width of the memory device. That is, if the memory device has a data width of eight bits, an output data path will be provided to only eight of the 128 bits. Such an arrangement can also allow “prefetch” architectures. In a prefetch architecture, all 128 memory cells would be accessed simultaneously, with data paths being provided sequentially according to the data width of the device. For example, in a read operation for a memory device having a 32-bit data width, data from 128 memory cells would be accessed in a single cycle, and then output, 32-bits at a time, on four consecutive clock cycles.
While semiconductor device manufacturing processes continue to improve, at the same time, dimensions continue to shrink and operating speeds continue to increase. Thus, in an attempt to create smaller and faster devices, manufacturing defects can still occur. In order to ensure that defective devices are not supplied to customers, semiconductor devices are usually tested to ensure their functionality. Many such tests involve writing data into and then reading data from, each of the memory cells within the semiconductor memory device. Due to the considerable number of memory cells within a semiconductor memory device, if such tests are undertaken using conventional access operations, a large amount of time is required to test each memory cell in the memory device.
In order to reduce the amount of time required to test a semiconductor memory device, many memory devices include “on-chip” test circuits. That is, rather than have test equipment generate all of the possible addresses and compare the resulting data with test data, circuits on the memory device itself can test memory cells, and provide data outputs reflecting the results of the test. An example of a prior art on-chip test arrangement for a semiconductor memory device is set forth in FIG.
1
.
Referring now to
FIG. 1
, a prior art semiconductor memory device having an on-chip test circuit is designated by the general reference character
100
. The memory device
100
is shown to include a corearray
102
which has a number of memory cells arranged into one or more arrays. The prior art memory device
100
of
FIG. 1
is a synchronous dynamic random access memory (DRAM), and so receives conventional input signals, including a system clock signal (CLK), a row address strobe signal (RAS_), a column address strobe signal (CAS_), a write enable signal W_, and address signals (ADD). The input signals are received by a command decoder
104
. The command decoder
104
generates internal control signals, including an internal row address strobe signal (INT_RAS), an internal column address strobe signal (INT_CAS), and internal address signals (INT_ADD). In addition, the command decoder
104
generates a test mode signal (TEST_MODE), an output enable signal (OE
0
), and an internal clock signal (INT_CLK).
According to the applied control signals, the corearray
102
provides access to selected memory cells by way of a number of data I/O lines (I/O
0
-I/O
7
). In the arrangement of
FIG. 1
, particular memory cells are accessed by the INT_ADD signals according to timing established by the INT_RAS and INT_CAS signals. The data I/O lines (I/O
0
-I/O
7
) are coupled to a standard data path
106
and a test data path
108
. To avoid unduly cluttering the view of
FIG. 1
, the standard data path
106
illustrates the data path for line I/O
0
only. The standard data path
106
is shown to include a data state circuit
110
. The data state circuit
110
receives a standard enable signal STD_EN signal and the I/O
0
line as inputs, and provides a standard data signal output DATA_STD. When the OE
0
signal is high, the data state circuit
110
drives its output DATA_STD according to the I/O
0
line signal. When the STD_EN signal is low, the date state driver is placed in a high impedance (hi-Z) state.
The output of the data state circuit
110
is connected to the input of a complementary metal-oxide-semiconductor (CMOS) transfer gate
112
. The transfer gate
112
, when enabled, provides a data input (DATA) to an output driver circuit
114
. The transfer gate
112
is enabled by a READ_CLK signal, and its complement, READ_CLK_.
The output driver circuit
114
also receives a driver output enable signal (OE). When the OE signal is high, the output driver circuit
114
drives a data output (DQ) according to the value of the DATA signal. When the OE signal is low, the output driver circuit
114
is placed in a hi-Z state. The output driver
114
set forth in
FIG. 1
is shown to include a CMOS driver stage that includes a p-channel MOS transistor P
100
and an n-channel MOS transistor N
100
. The operation of the two transistors (P
100
and N
100
) is controlled by NAND gate G
100
, NOR gate G
102
, and inverter I
100
. The DATA signal is received as an input to gates G
100
and G
102
, and the OE signal is connected directly to gate G
100
as a second input, and by way of inverter I
100
as a second input to gate G
102
. In this arrangement, when the OE signal is low, the output of gate G
100
is high and the output of gate G
102
is low, resulting in transistors P
100
and N
100
being turned off. When the OE signal is high, in the event the DATA signal is high, transistor P
100
is turned on, and transistor N
100
is turned off. In the event the DATA signal is low, transistor P
100
is turned off and transistor N
100
is turned on.
The STD_EN signal, the READ_CLK and READ_CLK_ signals are provided by a control circuit
116
. In a standard mode of operation (such as a read operation), the STD_EN signal is high and the READ_CLK and READ_CLK_ signals will pulse high and low, respectively. Consequently, as data is placed on the I/O
0
line, the data state circuit
110
will drive its output according to the logic of line I/O
0
. Transfer gate
112
will be turned on, resulting in the DATA signal being generated from the logic of line I/O
0
. The DATA signal will then result in a DQ signal having the same logic as the DATA signal.
The STD_EN, READ_CLK and READ_CLK_ signals are generated by the control circuit
116
in response to the TEST_MODE signal, the OE
0
signal, and the INT_CLK signal. The control circuit
116
is shown to include an inverter I
102
, a three-input AND gate G
104
, a two-input AND gate G
106
, and a two input NAND gate G
108
. The outputs of gates G
104
and G
106
provide inputs to a two-input OR gate G
110
. Gate G
104
receives the OE
0
signal and TEST_MODE signal as inputs, and in addition, receives a pass/fail indication (PASS) from the test data path
108
. In a non-test operation (such as a standard read operation), the TEST_MODE signal is low, thus gate G
104
provides a low output signal regardless of the state of its other inputs. The TEST_MODE signal is inverted by inverter I
102
and applied as one input to gate G
106
. The other input to gate G
106
is the OE
0
signal. In this manner, in a non-test mode, gate G
106
provides an output that reflects the value of OE
0
signal. The output of gate G
106
is the STD_EN signal.
The outputs of gates G
104
and G
106
are further provided as

Affiliated with

Also associated with

Rating

Two pass multi-state parallel test for semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two pass multi-state parallel test for semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two pass multi-state parallel test for semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2892136