Uniform testing of tristate nets in logic BIST

Details Uniform testing of tristate nets in logic BIST Uniform testing of tristate nets in logic BIST

2005-07-19

2005-07-19

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

06920597

ABSTRACT:
A built-in-self-test (BIST) circuit is discussed for selecting tristate nets with substantially uniform distribution using a tristate testing control device (TTCD). The circuit allows the deterministic testing of tristate nets in the context of pseudo-random BIST. A feedback shift register is described that activates a single tristate or set of tristate at a time in order to avoid bus contention. Another TTCD embodiment uses a counter and decoder. A test mode switching unit (TMSU) coupled between the TTCD and the tristate net selects test or functional mode for tristate enables. Parallel multiplexers are discussed as one embodiment of a TMSU. Another TMSU embodiment describes even better test coverage. A method, which may be performed on a distributed computer system, is discussed for identifying tristate nets within a net-list and adding a TTCD and a TMSU to the net-list.

REFERENCES:
patent: 5513190 (1996-04-01), Johnson et al.
patent: 5734581 (1998-03-01), Butts et al.
patent: 5774473 (1998-06-01), Harley
patent: 5949990 (1999-09-01), Mangelsdorf
patent: 6295636 (2001-09-01), Dupenloup
patent: 6493648 (2002-12-01), Anderson

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