Transmission device, reception device, test circuit, and...

Details Transmission device, reception device, test circuit, and... Transmission device, reception device, test circuit, and...

2006-02-28

2006-02-28

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S701000

Reexamination Certificate

active

07007212

ABSTRACT:
The present invention provides a transmission device, a reception device, a test circuit and a test method, which enable internal parts of the circuit to operate at high speed, while performing inputting/outputting to/from a tester at low speed. The test circuit comprises a PLL111which divides the frequency of a test clock input from the tester to generate a PLL clock CKp1, a FIFO113which stores input data input from the tester on the test clock and outputs the data on the PLL clock CKp1, an encoder114which distributes bits of the input data, a driver115which transmits the output signal from the encoder114to the outside, a PLL121which divides the frequency of the test clock to generate a PLL clock CKp2, a decoder124which arranges the bits of the signal received by a receiver123.

REFERENCES:
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patent: 6055658 (2000-04-01), Jaber et al.
patent: 6343366 (2002-01-01), Okitaka
patent: 6668237 (2003-12-01), Guccione et al.
patent: 09261692 (1997-10-01), None

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