Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2004-10-01
2008-08-12
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S023000, C326S041000, C365S189040, C716S030000
Reexamination Certificate
active
07412635
ABSTRACT:
Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device such as a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the automated testing procedure terminates, and the programmed IC begins to function according to the user design as determined by the last programmed bitstream.
REFERENCES:
patent: 4899067 (1990-02-01), So et al.
patent: 5153880 (1992-10-01), Owen et al.
patent: 5255227 (1993-10-01), Haeffele
patent: 5349248 (1994-09-01), Goetting et al.
patent: 5430734 (1995-07-01), Gilson
patent: 5434514 (1995-07-01), Cliff et al.
patent: 5459342 (1995-10-01), Nogami et al.
patent: 5485102 (1996-01-01), Cliff et al.
patent: 5498975 (1996-03-01), Cliff et al.
patent: 5513144 (1996-04-01), O'Toole
patent: 5592102 (1997-01-01), Lane et al.
patent: 5689516 (1997-11-01), Mack et al.
patent: 5742556 (1998-04-01), Tavrow et al.
patent: 5761483 (1998-06-01), Trimberger
patent: 5764577 (1998-06-01), Johnston et al.
patent: 5777887 (1998-07-01), Marple et al.
patent: 5796750 (1998-08-01), Lottridge et al.
patent: 5925920 (1999-07-01), MacArthur et al.
patent: 5931959 (1999-08-01), Kwiat
patent: 6003150 (1999-12-01), Stroud et al.
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6166559 (2000-12-01), McClintock et al.
patent: 6167558 (2000-12-01), Trimberger
patent: 6201404 (2001-03-01), Reddy et al.
patent: 6202182 (2001-03-01), Abramovici et al.
patent: 6247147 (2001-06-01), Beenstra et al.
patent: 6279146 (2001-08-01), Evans et al.
patent: 6289292 (2001-09-01), Charlton et al.
patent: 6292925 (2001-09-01), Dellinger et al.
patent: 6311316 (2001-10-01), Huggins et al.
patent: 6344755 (2002-02-01), Reddy et al.
patent: 6496971 (2002-12-01), Lesea et al.
patent: 6530071 (2003-03-01), Guccione et al.
patent: 6560740 (2003-05-01), Zuraski, Jr. et al.
patent: 6594610 (2003-07-01), Toutounchi et al.
patent: 6618686 (2003-09-01), Allamsetty
patent: 6664808 (2003-12-01), Ling et al.
patent: 6668237 (2003-12-01), Guccione et al.
patent: 6681353 (2004-01-01), Barrow
patent: 6704889 (2004-03-01), Veenstra et al.
patent: 6725442 (2004-04-01), Cote et al.
patent: 6744274 (2004-06-01), Arnold et al.
patent: 6779133 (2004-08-01), Whetsel
patent: 6864710 (2005-03-01), Lacey et al.
patent: 6915503 (2005-07-01), Lesea
patent: 6918027 (2005-07-01), Mantey et al.
patent: 6925407 (2005-08-01), Duppong
patent: 6961884 (2005-11-01), Draper
patent: 6973608 (2005-12-01), Abramovici et al.
patent: 7007250 (2006-02-01), Bapat et al.
patent: 7071679 (2006-07-01), Sabih et al.
patent: 7080300 (2006-07-01), Herron et al.
patent: 7127697 (2006-10-01), Wells et al.
patent: 7133822 (2006-11-01), Jacobson
patent: 7146598 (2006-12-01), Horanzy
patent: 7185293 (2007-02-01), Ofer
patent: 7216277 (2007-05-01), Ngai et al.
patent: 2001/0037458 (2001-11-01), Kean
patent: 2003/0078752 (2003-04-01), Allamsetty
patent: 2003/0097551 (2003-05-01), Fuller et al.
patent: 2003/0122578 (2003-07-01), Masui et al.
patent: 2003/0212940 (2003-11-01), Wong
patent: 2003/0225955 (2003-12-01), Feldstein et al.
patent: 2004/0010739 (2004-01-01), Odom et al.
patent: 2004/0138845 (2004-07-01), Park et al.
patent: 2004/0193979 (2004-09-01), Avery et al.
patent: 2004/0193980 (2004-09-01), Avery et al.
patent: 2005/0050393 (2005-03-01), Chakraborty et al.
patent: 2005/0125512 (2005-06-01), Fuller et al.
patent: 2005/0177251 (2005-08-01), Duppong
patent: 2005/0245098 (2005-11-01), Cooney et al.
patent: 2005/0246520 (2005-11-01), Vaid et al.
patent: 2006/0253266 (2006-11-01), Ong
patent: 2006/0259871 (2006-11-01), Washington et al.
patent: 2006/0282733 (2006-12-01), Whetsel
U.S. Appl. No. 10/956,556, filed Oct. 1, 2004, Trimberger.
U.S. Appl. No. 10/956,990, filed Oct. 1, 2004, Trimberger.
U.S. Appl. No. 10/957,261, filed Oct. 1, 2004, Trimberger.
U.S. Appl. No. 10/085,305, filed Feb. 28, 2002, Trimberger.
U.S. Appl. No. 10/104,324, filed Mar. 22, 2002, Wells et al.
U.S. Appl. No. 10/714,380, filed Oct. 31, 2003, Trimberger.
U.S. Appl. No. 10/717,040, filed Nov. 18, 2003, Ngai et al.
U.S. Appl. No. 10/813,414, filed Mar. 26, 2004, Stassart et al.
John Emmert et al.; “Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration”; Annual IEEE Symposium on Field-Programmable Custom Computing Machines; Apr. 17, 2000; pp. 165-174.
John M. Emmert et al.; “Incremental Routing in FPGAs”; ASIC Conference 1998. Proceedings, Eleventh Annual IEEE International; Rochester, NY; Sep. 13-16, 1998; pp. 217-221.
Xilinx, Inc.; “Virtex-II Pro Platform FPGA Handbook”; published Dec. 6, 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 33-75.
W. Bruce Culberston et al.; “Defect Tolerance on the Teramac Custom Computer”; The 5th Annual IEEE Symposium on Field-Programmabel Custom Computing Machines; Apr. 16-18, 1997; pp. 116-123.
Fran Hanchek et al.; “Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs”; The Proceedings of the Ninth International Conference on VLSI Design; Jan. 1996; pp. 1-4.
Altera; Altera Data Sheet, vol. I, Chapter 3 “Configuration and Testing”; and vol. 2 Chapter 8 “Remote System Upgrades with Stratix II Devices”; Feb. 2004; downloaded on Jun. 17, 2004 freom http://www.altera.com/literature/lit-stx2.
Cartier Lois D.
Louis-Jacques Jacques
Maunu LeRoy D.
Merant Guerrier
Xilinx , Inc.
LandOfFree
Utilizing multiple bitstreams to avoid localized defects in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Utilizing multiple bitstreams to avoid localized defects in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Utilizing multiple bitstreams to avoid localized defects in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4016513