Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-11-22
2005-11-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C703S004000, C716S030000
Reexamination Certificate
active
06968487
ABSTRACT:
A method of accessing the testing means in a Field Programmable Gate Array (“FPGA”) comprised of a plurality of functional groups (“FGs”) comprising: inputting a function netlist defining a user circuit; compiling said function netlist; and generating a logic Built-In Self Test (“BIST”) netlist; wherein said BIST netlist replaces all user registers with scan registers with a scan chain routed as the physical silicon scan chains.
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Bryant Ian
Chan Stephen
Feng Sheng
Lien Jung-Cheun
Sun Chung-Yuan
Actel Corporation
Britt Cynthia
De'cady Albert
Sierra Patent Group Ltd.
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