Timing generator for testing semiconductor storage devices

Details Timing generator for testing semiconductor storage devices Timing generator for testing semiconductor storage devices

1997-05-29

2000-05-09

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714743, G01R 3128

Patent

active

060618167

ABSTRACT:
A timing generator operates in response to test cycles to generate test pulses for testing of semiconductor storage devices. For example, the timing generator is designed to generate two test pulses with respect to each test cycle. Herein, a RAM stores timing data under the control of a CPU. When reading the timing data from the RAM, the timing generator receives a reference clock signal, on which clock pulses repeatedly occur by a certain period in synchronization with the test cycles, to produce a clock signal which contains two pulses with respect to each test cycle. Two read addresses are sequentially generated based on the reference clock signal and clock signal. Each read address is represented by a binary code consisting of a number of bits, one of which is inverted in response to the clock signal. So, two timing data are sequentially read from the two read addresses of the RAM with respect to each test cycle. A pulse generator receives the two timing data to generate two test pulses with respect to each test cycle. Herein, generation of the two test pulses is initiated when a time represented by the timing data elapses from a trigger signal, whilst a constant interval of time is provided between the two test pulses, regardless of the test cycles.

REFERENCES:
patent: 4730318 (1988-03-01), Bogholtz, Jr. et al.
patent: 5390192 (1995-02-01), Fujieda
patent: 5651014 (1997-07-01), Kobayashi

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