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System and method for implementing postponed quasi-masking...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for improving LBIST test coverage

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for improving transition delay fault...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for improving transition delay fault...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for increasing error checking performance...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for input/output characterization

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for intelligent analysis probe

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for model size reduction of an integrated circ

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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System and method for optimized test and configuration...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for optimized test and configuration...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for parallel testing of IEEE 1149.1...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for performing class propagation and type chec

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for performing high speed memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for performing improved pseudo-random testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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System and method for performing logic failure diagnosis...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for performing predictable signature...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for performing scan test with single scan...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for power reduction through power aware...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for power reduction through power aware...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and method for providing secure boundary scan...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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