System and method for model size reduction of an integrated circ

Details System and method for model size reduction of an integrated circ System and method for model size reduction of an integrated circ

1997-01-27

2000-04-11

Teska, Kevin J.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

39550038, 39550023, 714 33, G06F 1750

Patent

active

060496622

ABSTRACT:
The present invention provides a system and method for verifying an integrated circuit model. The model includes a plurality of net variables. The system and method comprises generating a plurality of tests for simulating the integrated circuit, precalculating a reduced model based upon the generated tests, and evaluating the reduced model. In a preferred embodiment, the present invention includes restricting the test that are generated. Then net invariants for the integrated circuit are generated by translating the restricted plurality of tests to a smaller set of possible values for the net variables. Thereafter, a minimization algorithm or procedure is utilized to minimize the logic used in the particular system based upon the latch constraints. This system produces a reduced model which reduces the amount of the integrated circuit that must be simulated thereby increasing the simulation speed thereof. Accordingly, the present invention integrates an event-driven simulation and a cycle simulation in such a manner that the saving can be proportional to the size of the reduction of the model. In many environments this reduction is significant because it allows for a significant reduction in space which has a clear bearing on the verification process.

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