Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1993-06-28
1999-09-14
Stamber, Eric B.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714734, G01R 3128
Patent
active
059517034
ABSTRACT:
A digital system includes a number of digital subsystems interconnected by a shared bus structure that is mutually exclusively accessible for communicating data between the subsystems. The system is structured to be tested by pseudo-random scan test methodology. Each subsystem includes a counter that, during scan test periods, provides an enable signal to the bus access or driver circuitry of the associated subsystem. A scan test operation is preceded by pre-loading each counter with a predetermined state so that, initially, and throughout the test period, one and only one digital subsystem will drive the shared data bus. Each scan sequence (comprising a scan in, an execution cycle, and a scan out of the pseudo-random test strings) will result in the counters being clocked once so that a new subsystem will be enable to drive the bus the next sequence, permitting the bus access circuitry of each subsystem, and the bus itself, to be tested.
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Gibson Walter E.
Sprouse Jeffrey A.
Stamber Eric B.
Tandem Computers Incorporated
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