Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-04-12
2011-04-12
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S729000, C714S742000, C324S763010, C324S765010
Reexamination Certificate
active
07925948
ABSTRACT:
A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
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Goodman Benjiman L.
Hernandez Joshua P.
Ward Samuel I.
Ward, Jr. Linton B.
Caldwell, Esq. Patrick E.
International Business Machines - Corporation
Tabone, Jr. John J
The Caldwell Firm, LLC
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