Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-08
2008-07-08
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
07398441
ABSTRACT:
The present invention is a method including: receiving an input key string; comparing the input key string with a stored key string; and granting access to a boundary scan chain when the input key string matches the stored key string, the boundary scan chain being at least one of: a Boundary Data Register of at least one Joint Test Action Group (JTAG)-compliant device; or, a plurality of communicatively coupled JTAG-compliant devices.
REFERENCES:
patent: 5457408 (1995-10-01), Leung
patent: 5894213 (1999-04-01), Nakamura
patent: 6574762 (2003-06-01), Karimi et al.
patent: 7274283 (2007-09-01), Yosim et al.
Chung Phung M
Eppele Kyle
Jensen Nathan O.
Rockwell Collins, Inc.
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