Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-02-18
2002-08-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06442725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The resent invention generally relates to a system and method for providing intelligence to an analysis probe being utilized by logic analyzers. Specifically, the system and method of the present invention provide for regenerating data signals for analysis by a logic analyzer from data lines that are being utilized for other purposes by a target system processor.
2. Description of Related Art
As is known in the computer and software arts, when a new computer hardware and software system is developed, the system will exhibit errors. As a consequence, developers of the hardware and software systems utilize many techniques in which to check the correctness of the hardware and software and to diagnose these errors.
One of the devices that developers will often use to debug electronics is a logic analyzer. The use of logic analyzers has never been easy. One of the most difficult tasks when using a logic analyzer has been probing the device under test. Many logic analyzer vendors have dealt with this issue by providing an accessory that simplifies the task of connecting the logic analyzer to the device under test (oftentimes, a microprocessor). This device is usually called an “analysis probe.”
Analysis probes usually connect to the device under test or test system with one connection that probes all desired signals at once. The user then connects a few logic analyzer adapter cables to the logic analyzer, rather than numerous individual probes. The use of an analysis probe also provides the user with inverse assembly functionality. The inverse assembly functionality consists of monitoring the signals on the processor to determine the processor instruction flow. This processor instruction flow denotes exactly what instructions are being processed on the processor at any given time. The processor instructions also include information as to what registers and memory addresses are being accessed. In order to get the inverse assembly functionality, certain data signals require probing by the logic analyzer.
Because microprocessor chip designers are continuing to integrate peripherals within the microprocessors themselves, signals necessary for inverse assembly functionality are neither being routed to pins of the package nor being multiplexed with other signals. The non-routing of signals makes it difficult for the logic analyzer to convert the signals necessary for inverse assembly into disassembly mnemonics. Disassembly mnemonics consists of constructing the instruction symbol that can represent processor instructions and operations, such as “add” (for addition) and “sub” (for subtraction).
A common example case where this occurs is the replacing of an upper address line with a write enable (i.e. chip select) when the chip select is being used. The logic analyzer needs all address lines in order to determine where the processor is executing code or reading or writing memory. If the microprocessor has a write enable (i.e. chip select) signal in place of an upper address line, the inverse assembler functionality is unable to operate on the addresses that the logic analyzer needs to generate the inverse assembly. In addition, the user is unable to view the correct address in the inverse assembler. If a user wishes to view the correct address, they cannot use the write enable (i.e. chip select) signals. Users find this extremely inconvenient since the write enable (i.e. chip select) signals are directly tied to the hardware system.
Heretofore, software developers have lacked a system and method for regenerating data signals for analysis by a logic analyzer from data lines that are being utilized for other purposes by a target system processor.
SUMMARY OF THE INVENTION
The present invention is generally directed to a system and method for regenerating internal data signals from external data lines that are being utilized for other functions by a target system processor. This allows a logic analyzer to display data signals that are actually being utilized internally by a target processor. Data signal reconstruction uses the target processor's chip selects, address, and data lines to recreate the desired internal data signals. This reconstruction is accomplished so the desired data signals can be viewed by a logic analyzer if the target processor is utilizing the desired data signal lines for tasks other than the desired data signals transmission.
The present invention further utilizes a system and method where an emulation module that allows a user to configure the analysis probe to enable data reconstruction for a variety of different target system processor configurations.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.
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Adams Steven Wayne
Call, Jr. O Bryan
Dotseth Michael Jon
Greenley Gordon A
Schipke Brian Clay
Agilent Technologie,s Inc.
De'cady Albert
Torres Joseph D.
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