Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-29
2008-07-29
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
10896646
ABSTRACT:
A system and method for maximizing the throughput of test and configuration in the manufacture of electronic circuits and systems. The system employs a tester having a flexible parallel test architecture with expandable resources that can accommodate a selected number of units under test (UUTs). The parallel test architecture is configurable to accept separate banks or partitions of UUTs, thereby enabling the system to obtain an optimal or maximum achievable throughput of test and configuration for the UUTs. The system determines an optimal or maximum achievable throughput by calculating a desired number N of UUTs to be tested/configured in parallel. Testing or configuring this desired number of UUTs in parallel allows the handling time to be balanced with the test and configuration times, thereby resulting in the maximum achievable throughput.
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Medthod and Apparatus for Optimized Parallel Testing and Access of Electronic Circuits. Ricchetti et al. U.S. Appl. No. 10/119,060, filed Apr. 9, 2002.
Clark Christopher J.
Ricchetti Michael
Britt Cynthia
Intellitech Corporation
Merant Guerrier
Weingarten Schurgin, Gagnebin & Lebovici LLP
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