System and method for improving transition delay fault...

Details System and method for improving transition delay fault... System and method for improving transition delay fault...

2005-05-06

2008-12-02

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07461307

ABSTRACT:
The present invention is directed to a system and method for improving transition delay test coverage through use of enhanced flip flops (ES flip-flops) for a broadside test approach. Each ES flip-flop includes a two port flip-flop including a first flip-flop and a second flip-flop. A separate control input (ESM) which is not time critical is used to select a multiplexer of the second flip-flop. Thus, the ES flip-flops do not require a fast signal switching between launch and test response capture or an extra clock signal. Various enhanced scan modes may be selected via a combination of SEN and ESM. Moreover, only a heuristically selected subset of scan flip-flops may be replaced with the ES flip-flops so as to minimize the length of a scan chain as well as the logic area overhead. The present invention provides high TDF coverage under the broadside testing.

REFERENCES:
patent: 4602210 (1986-07-01), Fasang et al.
patent: 5682391 (1997-10-01), Narayanan
patent: 6023778 (2000-02-01), Li
patent: 6122762 (2000-09-01), Kim
patent: 6806731 (2004-10-01), Kohno
patent: 2004/0177299 (2004-09-01), Wang et al.
patent: 2005/0216806 (2005-09-01), Verwegen

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