Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-04-13
2003-09-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
06618827
ABSTRACT:
TECHNICAL FIELD
The present invention is generally related to system and method for conducting parallel testing of IEEE 1149.1 compliant integrated circuits hardware via comparing results generated by integrated circuits under evaluation in accordance with IEEE 1149.1 JTAG/IEEE standard test access port and boundary scan architecture provisions, with a master reference signal to determine whether the integrated circuit is functioning properly.
BACKGROUND OF THE INVENTION
It is common for integrated circuits to be tested and/or evaluated using standard test access port provisions complying with the IEEE 1149.1 (JTAG) standard. JTAG compliant integrated circuits provide for a four wire test access port (test bus), or TAP, which is used to convey serial-test information to the integrated circuit. The TAP provides for a system clock (synchronization) signal TCK, a state control signal TMS, a test data input signal TDI and a test data output signal TDO. Test instructions, test data and test control signals all are passed along to the TAP. The TAP controller of the IEEE 1149.1 compliant integrated circuit monitors two signals from the TAP bus master. These are the synchronization signal (TCK) and the state control signal (TMS). The TAP bus master can be an external test system such as automatic test equipment (ATE) or an embedded system that might be part of a system maintenance architecture.
In order to test each JTAG compliant integrated circuit, it is necessary for the TAP of each integrated circuit to be provided with test instructions, test data and test control signals. The test data output (TDO) of each integrated circuit is then read out and compared with expected results. The expected results may be predetermined or calculated by the TAP bus master. Where TDO is compared and determined to be the same as the expected results, it is then known that the integrated circuit under evaluation is functioning properly. Likewise, where TDO is determined to be different than TDI, it is then known that the integrated circuit under evaluation is not functioning properly.
Where there are large numbers of identical integrated circuits in a system which require testing via the same test instructions, test data and test control signals, each integrated circuit typically is individually tested one after the other. As the number of integrated circuits to be tested increases, so does the time required to carry out such testing activities.
Integrated circuits can be tested concurrently. However, this requires additional separate test systems to test each integrated circuit within the system at the same time. This does save time, however due to the necessary replication of test systems for each integrated circuit, or type of integrated circuit, to be tested and it can be expensive and require additional floor space to accommodate the replicated testing systems.
SUMMARY OF THE INVENTION
The present invention provides an apparatus and technique for providing parallel testing of multiple IEEE 1149.1 compliant integrated circuits. Briefly described, in architecture, the system can be implemented as follows. A preferred embodiment of the present invention incorporates a chain select unit for receiving test data signal output from an integrated circuit under evaluation. A delay adjustment unit is provided for synchronizing the received test data signal with a reference signal as may be needed to account for propagation (link) delays between the device under test and the test unit; and a comparator unit is provided for comparing the received test data signal with a master reference signal to determine if the signals are the same or not. The master reference signal can be, for example, a selected output from one of the multiple IEEE 1149.1 compliant integrated circuits being tested. Further, the master reference signal could be another predetermined signal source.
The present invention can also be viewed as providing a method for providing identification information to a connected system that requires such identification information. In this regard, the method can be broadly summarized by the following steps: receiving input of test data from a plurality of IEEE 1149.1 compliant integrated circuits, and; simultaneously comparing the received input test data with a master reference signal to determine if the received input test data is the same as the master reference signal.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.
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Chaudry Mujtaba
De'cady Albert
Hewlett--Packard Development Company, L.P.
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