Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-11-06
2007-11-06
Lamarre, Guy (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C326S016000
Reexamination Certificate
active
11124438
ABSTRACT:
The present invention is directed to a system and method for improving transition delay fault coverage through use of augmented flip-flops (TL flops) for a broadside test approach. The TL flops use the same clock for scan and functional operation. Thus, the TL flops do not require a fast signal switching between launch and test response capture. Each of the TL flops includes additional multiplexer in front of a standard scan flop and a transition enable (TEN) signal. Moreover, only a heuristically selected subset of scan flip-flops is replaced with the TL flops and only one additional MUX per selected scan flip-flop may contribute an area overhead. Consequently, the overall chip area overhead may be minimal. The present invention may be suitable for being implemented with currently available third party ATPG.
REFERENCES:
patent: 6108805 (2000-08-01), Rajsuman
patent: 6148425 (2000-11-01), Bhawmik et al.
patent: 6611932 (2003-08-01), How et al.
patent: 7039845 (2006-05-01), Rearick et al.
patent: 7131081 (2006-10-01), Wang et al.
Devta-Prasanna Narendra
Gunda Arun
Abraham Esaw T.
Lamarre Guy
LSI Corporation
Suiter - West - Swantz PC LLO
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