Rapid fail analysis of embedded objects

Details Rapid fail analysis of embedded objects Rapid fail analysis of embedded objects

2005-08-16

2005-08-16

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000, C382S149000

Reexamination Certificate

active

06931580

ABSTRACT:
A method for analyzing test data for objects on an IC or a wafer is provided. The test data is linked to available layout information about the object under test. Certain objects are selected based on the test data. A representation of the selected objects is placed on a map of the IC or on a map of the wafer. The representation should correspond to the physical location of the object on the IC or wafer. Preferably, the representation comprises one or more polygons that enclose all devices that make up the object.

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