Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-02-04
2008-07-15
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S700000
Reexamination Certificate
active
07401273
ABSTRACT:
A data processing apparatus and method are provided for recovering from errors in the data processing apparatus. The data processing apparatus comprises processing logic operable to perform a data processing operation, and a plurality of sampling circuits, each sampling circuit being located at a predetermined point in the processing logic and operable to sample a value of an associated digital signal generated by the processing logic at that predetermined point. Each of the sampling circuits includes a backup latch for storing a backup copy of the associated digital signal value, and at least one of the sampling circuits is operable to temporally sample the value of the associated digital signal at a first time and at at least one later time, and to store as a backup copy a selected one of the sampled values representing a correct value. The value of the associated digital signal sampled at the first time is initially output from that sampling circuit, and that sampling circuit is operable to determine an occurrence of an error in the value of the associated digital signal sampled at the first time, and to issue an error signal upon determination of that error. The data processing apparatus further comprises error recovery logic operable in response to the error signal to implement a recovery procedure during which selected sampling circuits output as their sampled associated digital signal value the value stored in their backup latch.
REFERENCES:
patent: 5504859 (1996-04-01), Gustafson et al.
patent: 5553232 (1996-09-01), Wilhite et al.
patent: 6772388 (2004-08-01), Cooper et al.
patent: 6799292 (2004-09-01), Takeoka et al.
patent: 6834367 (2004-12-01), Bonneau et al.
patent: 7085993 (2006-08-01), Goodnow et al.
patent: 7162661 (2007-01-01), Mudge et al.
N Kanekawa et al, “Fault Detection and Recovery Coverage Improvement by Clock Synchronized Supplicated Systems with Optimal Time Diversity” Fault-Tolerant Computing, Jun. 1998, pp. 196-200.
D. Mavis et al., “Soft Error Rate Mitigation Techniques for Modern Micorcircuits”, 40thAnnual International Reliability Physics Symposium, Dallas, Texas 2002, pp. 216-225.
Austin Todd Michael
Lee Seokwoo
ARM Limited
Britt Cynthia
Nixon & Vanderhye P.C.
University of Michigan
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