Reconstruction of non-deterministic algorithmic tester...

Details Reconstruction of non-deterministic algorithmic tester... Reconstruction of non-deterministic algorithmic tester...

2007-02-20

2007-02-20

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

10206264

ABSTRACT:
Input to a device under test (DUT) is reconstructed. For each trigger cycle of a tester in which data is to be input to the DUT stimulus, data is prepared to be placed as stimulus on pins of the DUT. Response information obtained from the DUT during a previous trigger cycle is used to construct formatting information used to adjust a value of the stimulus data. Reconstruction information sufficient to reconstruct the stimulus data is stored. The reconstruction information includes the formatting information. The reconstruction information is used to reconstruct the stimulus data placed on the pins of the device under test.

REFERENCES:
patent: 5680518 (1997-10-01), Hangartner
patent: 5748642 (1998-05-01), Lesmeister
patent: 6282134 (2001-08-01), Kumar
patent: 6681351 (2004-01-01), Kittross et al.
patent: 2004/0006447 (2004-01-01), Gorin
Agilent 93000 SOC Series User Training Part 1, Revision 2.2, available from Agilent Technologies, Inc. as Part No. 5968-5522E, 2000, pp. 274-278.

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