Reduced pattern memory in digital test equipment

Details Reduced pattern memory in digital test equipment Reduced pattern memory in digital test equipment

2006-03-28

2008-10-07

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000

Reexamination Certificate

active

07434124

ABSTRACT:
A test system and method of configuring therefor. A test system includes a plurality of interface circuits for communicating with a device under test (DUT). The test system further includes a first memory for storing test vectors, a second memory for storing selection codes, and a third memory for storing configuration sets. Each selection code indicates an association between a test vector and a configuration set. Each configuration set may be associated with one or more of the test vectors. The configuration sets include information for configuring the interface circuits during communications between the test system and the DUT for each test vector. Each configuration set in the third memory is unique with respect to the other configuration sets, and the number of configuration sets may be less than the number of test vectors.

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