Reconstruction engine for a hardware circuit emulator

Details Reconstruction engine for a hardware circuit emulator Reconstruction engine for a hardware circuit emulator

1998-06-12

2000-05-09

Teska, Kevin J.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

39550044, 714 47, G06F 9455

Patent

active

060615117

ABSTRACT:
A system and a method provide full visibility to each net of a design under modeling by saving states of the design during modeling and reconstructing waveforms at each net by logic evaluation using the saved states. In one embodiment, primary data input signals and memory output signals ("sample signals") are saved by a logic analyzer, and used in an emulator to generate state vectors from a state snapshot previously recorded. Data compression techniques can be applied to minimize storage requirements, and parallel evaluation of segments of waveforms can be achieved, since saved states for the entire period of interest are available for waveform reconstruction at the time of the logic evaluation.

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