Reduced pin count scan chain implementation

Details Reduced pin count scan chain implementation Reduced pin count scan chain implementation

2005-12-19

2008-05-27

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07380185

ABSTRACT:
The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic circuit for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit, and for providing a scan data output signal; and wherein the scan data input signal and the scan data output signal share an input/output pin.

REFERENCES:
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patent: 5812561 (1998-09-01), Giles et al.
patent: 6125464 (2000-09-01), Jin
patent: 7219281 (2007-05-01), Dubey
patent: 7219282 (2007-05-01), Sunter et al.
patent: 2003/0041296 (2003-02-01), Bos et al.
patent: 2006/0248419 (2006-11-01), Colunga et al.

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