Random path delay testing methodology

Details Random path delay testing methodology Random path delay testing methodology

2000-12-22

2004-04-27

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S739000, C714S741000, C716S030000, C703S014000

Reexamination Certificate

active

06728914

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to testing of complex combinatorial and sequential logic circuits embodied in large scale integration (LSI) and very large scale integration (VLSI) circuit devices.
BACKGROUND OF THE INVENTION
A fault occurring anywhere in a LSI or VLSI circuit device can have its effect propagated through a number of feedback loops including storage or memory elements in the sequential logic before reaching a testable output of the device. Level sensitive scan design (LSSD) rules were devised to eliminate the complications in testing caused by this propagation through feedback loops. As described by E. B. Eichelberger and T. W. Williams in an article entitled “A Logic Design Structure for LSI Testability” on pages 462-468 of the Proceedings of the 14th Design Automation Conf., LSSD rules impose a clocked structure on logic circuit memory elements such as latches and registers, and require these memory elements be tied together to form a shift register scan path so that they are accessible for use as test input and output points. Therefore, test input signals can be introduced or test results observed wherever one of the memory elements occurs in the logic circuit. Being able to enter the logic circuit at any memory element for introducing test signals or observing test results, allows the combinational and sequential logic to be treated as much simpler combinational logic for testing purposes thus considerably simplifying test generation and analysis. Patents describing LSSD techniques include U.S. Pat. Nos. 3,783,254; 3,784,907; 3,961,252, 4,513,418 and 5,983,380. The subject matter of these patents and the above described Eichelberger and Williams article are hereby included by reference.
Self-testing has been employed in connection with LSSD to reduce the time it takes to generate the test patterns and to perform the testing. Self-testing involves the use of pseudo-random pattern generators and response compression structures that are built into logic circuit devices. Using such pattern generators and compression structures eliminates the computer time needed to generate the tests and placing these testing elements on the device containing the logic allows the application of vast numbers of test patterns to the circuits in a reasonable period of time.
In the aforementioned U.S. Pat. No. 5,983,380, the shift register latches (SRLs) in the LSSD scan paths perform both input data launching and output data capturing. The test patterns come from the scan path that is configured into a linear feedback shift register (LFSR). The test data is then outputted into a multiple input shift register (MISR) for data compression. Alternate scan path shift cycles are applied to the SRLs exercising the combinational logic with the contents of the SRLs and capturing the results of the response back into the SRLs where they are used as test inputs for the next cycle. At the end of a calculated number of cycles, the contents of the scan path are read out as the signature to be compared with the desired value. Such self-testing is referred to as Logic Built-In Self-Test (LBIST).
Two types of LBIST tests are applied. One is DC-LBIST which uses the stuck-at fault model to generate and simulate the patterns. Another is AC-LBIST which uses the transition fault model to generate and simulate the patterns. In present AC-LBIST test methodology, a series of pseudo random patterns generated from LFSR are fed to logic through SRLs, as described above. During AC-LBIST simulation, when a fault resulting from the application of the pseudo random patterns is detected at a capturing latch, it is marked off from the fault list. That is, the fault is marked off as long as it reaches the capturing latch no matter the length of the path it traveled. Very often that detecting path is a short rather than a long one. As VLSI technology has evolved, increasing chip complexity and speed and shrinking circuit dimensions have made such small AC defects a more serious impediment to proper operation of the circuits being tested.
Therefore, it is an object of the present invention to provide improved LSSD testing methods and apparatus.
It is another object of the present invention to provide for more efficient testing of logic circuits for small AC delay defects.
It is a further object of the invention to provide improved AC-LBIST testing.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the present invention for each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between input or launch SRL and output or capture SRL. The paths through the logic gate are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. A standard LBIST tool is used to apply pseudo random LBIST patterns to the logic circuit. When a fault associated with a logic gate is detected by a capture SRL of a path that is above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until all pseudo random testing patterns for the group falling below the threshold value are performed. When pseudo random testing of the group falling below the threshold is completed, a separate test generation program is activated. In the generated test, the test patterns are forced to propagate through the longest path that is above the threshold value to complete testing for the remaining faults.


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