Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2004-11-23
2008-10-28
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C713S193000, C713S500000, C713S400000, C713S401000, C714S733000, C714S735000, C714S048000, C714S738000, C714S799000, C714S736000, C714S742000, C714S811000, C714S815000, C714S797000
Reexamination Certificate
active
07444565
ABSTRACT:
A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output from each programmable logic component to a fixed logic component, examining the outputs, and determining a validated output from among the outputs. An architecture for mitigating logic upsets includes an input, a plurality of programmable logic components, and a fixed logic component. The input is provided to each of the programmable logic components. Each programmable logic components includes an encryption algorithm and a first majority voting logic, and processes the respective input to determine a respective output. The fixed logic component includes a second majority voting logic. The fixed logic component receives each respective output from the programmable logic components, examines the outputs, and determines a validated output.
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Edell Shapiro & Finnan LLC
ITT Manufacturing Enterprises Inc.
Louis-Jacques Jacques
Merant Guerrier
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