Real-time decoder for scan test patterns

Details Real-time decoder for scan test patterns Real-time decoder for scan test patterns

2000-04-12

2003-08-26

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

06611933

ABSTRACT:

FIELD OF THE INVENTION
This invention is related to scan testing of complex digital circuits including integrated circuits (ICs), higher level assemblies and systems using ICs, and more particularly, to a method and apparatus for expanding test patterns applied to a restricted number of product primary inputs to inputs of a larger number of on-product scan chains for the purpose of scan testing.
BACKGROUND OF THE INVENTION
Scan testing of digital circuits, internal sequential or register elements, such as latches, and the like, scattered between combinatorial components are designed in a way that they can be connected to each other in several parallel shift registers called scan chains. The inputs of the scan chains are connected to primary inputs (PIs) of the product under test. Each scan test typically requires that the scan chains be completely loaded with new test data one or more times using a scan load-operation. This loading operation takes place prior to applying a test sequence that exercises the logic connected to the register elements. The scan chains are loaded by repeatedly supplying a binary input data word with one bit of information for each scan chain followed by the application of one scan clock cycle. In response to the scan clock cycle, information already in the scan chains is shifted by one bit position towards the end of each chain. At the same time, the new information bit supplied at each scan chain input is loaded into the respective register element closest to each scan chain input. The number of scan clock cycles and input data words needed for completely loading all the scan chains is, thus, determined by the number of register elements in the longest scan chain.
The scan chains operate as clocked serial shift registers that are serially loaded with test input data (test stimulus data) from a suitable test stimulus data source. The procedure used for loading the scan chains is referred to as a scan-load operation. Automatic Test Equipment (ATE) is the most prevalent source of test stimulus data used for testing integrated circuits (IC) chips and higher-level assemblies. Once the test stimulus data has been loaded into the scan chains, the circuit under test can be exercised. These, in turn, result in certain test responses that are captured by the internal register elements that form the scan chains. The captured responses are, then, serially unloaded to a suitable test response sink for comparison with expected responses. ATE is one of such test response sinks. The procedure used for unloading is referred to as a scan-unload operation Data to be loaded is stored in the ATE and transferred to the component under test by shifting the scan chains. The total number of register elements in the component under test determines the amount of data needed for one complete load. The length of the longest scan chain and the shift cycle time determine the time needed for a complete load.
In order to reduce test time, it is advantageous to implement a large number of shorter scan chains rather than a small number of long chains. It should be noted that the use of more scan chains does not reduce by itself the total number of register elements and, hence, does not reduce the amount of data needed for a complete load. Furthermore, some scan tests may require more than one complete load to achieve fault detection. Hence, the total number of loads may exceed the number of tests in the full test program that must be applied to achieve the desired test coverage.
The number of register elements in modern ICs can exceed several hundred thousands. Thousands of scan tests-must be applied to achieve a good test coverage. In aggregate, the total amount of test data needed for a full test program begins to reach the limits of buffer storage available on a typical ATE used for a manufacturing test, even if the ATE is equipped with a dedicated scan buffer memory. Furthermore, typical ATEs often limit the maximum number of scan chains and the shift cycle rate. The fixed width and bandwidth of the scan interface result in longer scan chains and increased test time as the complexity of ICs grows with every new technology generation.
In conventional scan testing, test stimulus data is stored in ready-to-apply form in a high-speed buffer memory within the ATE and is directly loaded into the scan chains without additional data transformations. ATE architectures typically constrain the maximum of amount scan buffer memory available for scan test stimulus data, the maximum number of scan chains that can be serviced in parallel from a scan buffer memory, and the maximum cycle rate at which the data can be loaded into the scan chains. In other words, an ATE is characterized by a limited scan buffer space and a fixed, narrow bandwidth for transferring scan test stimulus data from ATE to the circuit under test.
Experience teaches that the number of register elements in a digital network grows proportionally with the size of the network, and that the number of tests also increases with network size. Consequently, the total amount of test stimulus data tends to grow more than linearly with network size and continuously threatens to exceed the buffer memory of installed ATEs, as new technology generations are introduced. Moreover, the limited bandwidth of existing ATE results in increasingly longer test times due to the larger amount of test stimulus data that must be applied to larger networks. An added area of concern is the time required to retrieve test data from archival storage, transfer it to the ATE, and load the data into the scan buffer memory. Combined, these trends contribute to a continuous degradation of throughput and productivity of the installed ATE with every new technology generation. It, further, results in a higher test cost due to longer test times and/or the need to invest in additional expensive ATE to increase the capacity of the manufacturing test floor. Further discussion of this problem can be found in the following two related articles:
“Bit-Flipping BIST” by Hans-Joachim Wunderlich and Gundolf Kiefer, published in ICCAD '96, pp. 337-346, 1996; and
“Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST”, by N. A. Touba and E. J. McCluskey, published in 1995 International Test Conference, pp. 174-682.
In both articles, the relative sparseness of care-bits for synthesizing custom logic that modifies data streams generated by an LFSR as needed for reconstructing the correct care-bit values is exploited. The disadvantage of these approaches is that the resulting custom logic is different for each design and constitutes an additional, unpredictable hardware overhead.
The present invention is based on a test data encoding concept published at the 1991 European Test Conference by Bernd Koenemann, in an article entitled “LFSR-Coded Test Patterns for Scan Designs”, pp.237-242. Several extensions of this scheme were subsequently published in academia and industry, e.g., by N. Zacharia et al., “Two-Dimensional Test Data Decompressor for Multiple Scan Designs”, 1996 International Test Conference, pp. 186-194; and by Pieter M. Trouborst, “LFSR Reseeding as a Component of Board Level Test”, 1996 International Test Conference, pp. 58-96.
In all prior approaches, a Linear Feedback Shift Register (LFSR) within the IC under test is used as a means for test data expansion. The disadvantage of these approaches is that the width of the on-chip LFSR determines how many seed bit values are available as independent variables for encoding each test. Hardware cost considerations limit a reasonable width of the LFSR, which in turn limits the number of care bits that can be successfully encoded in each test. The methods are also sub-optimal from a semiconductor manufacturing test point of view in that they do not exploit the available bandwidth of the ATE. The ATE loads a seed into the LFSR at the beginning of each test but, then, essentially sits idle for many scan clock cycles until the test has been expanded and shifted into the internal scan chains

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