Read only memory embedded in a dynamic random access memory

Details Read only memory embedded in a dynamic random access memory Read only memory embedded in a dynamic random access memory

1998-05-19

2000-11-28

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714718, 365201, G06F 1100

Patent

active

061548642

ABSTRACT:
The present invention is embodied in a method and apparatus which provides a ROM embedded in an DRAM utilizing unused portions of the DRAM. By hardwiring the unused digitlines of the DRAM to either a specified voltage or ground, the outputs of the sense amplifiers associated with those unused digitlines can be programmed to output a specific logic state. By combining the outputs from several sense amplifiers, a fixed bit pattern can be produced. The fixed bit pattern can be used, for example, to generate a test data pattern for a Built-in Self Test or to generate an initialization sequence.

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