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Method of micro-architectural implementation on bist fronted...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of outputting internal information through test pin...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of performing programming and diagnostic functions...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of performing programming and diagnostic functions...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of reducing test time for NVM cell-based FPGA

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of repairing integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing a circuit using an output vector

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing a multichip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing an integrated circuit having a flexible...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing and diagnosing field programmable gate arrays

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing at-speed circuits having asynchronous...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing circuit blocks of a programmable logic device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing circuit blocks of a programmable logic device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing logic devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method of testing multiple modules on an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing multiple modules on an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method on scan chain reordering for lowering VLSI power...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method tester and circuit for applying a pulse trigger to a unit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method to descramble the data mapping in memory circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method to locate logic errors and defects in digital circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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