Method to locate logic errors and defects in digital circuits

Details Method to locate logic errors and defects in digital circuits Method to locate logic errors and defects in digital circuits

2007-11-13

2007-11-13

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

11262084

ABSTRACT:
When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k−1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.

REFERENCES:
patent: 6442720 (2002-08-01), Koprowski et al.
patent: 6836867 (2004-12-01), Yonetoku
patent: 7111213 (2006-09-01), Dastidar et al.
Hasteer, G., et al., “An Efficient Assertion Checker for Combinational Properties”, Proceedings of the Design Automation Conf., Anaheim, Jun. 9-13, 1997, New York, ACM, vol. Conf. 43, Jun. 9, 1997.

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