Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-11
2001-08-07
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S765010, C324S762010, C326S038000, C326S041000, C326S044000
Reexamination Certificate
active
06272655
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is related to the field of the testing of integrated circuits and, more particularly, to the testing of NVM-based FPGAs (non-volatile memory-based field programmable gate arrays). The present invention is particularly suitable to flash memory-based FPGAs.
Typically, an FPGA is an array of logic elements and wiring interconnections with many thousands, or even hundreds of thousands, of programmable switches so that the FPGA can be configured by the user into an integrated circuit with defined functions. Each programmable switch, or interconnect, can connect two circuit nodes in the integrated circuit to make (or break) a wiring interconnection, or to set the function or functions of a logic element.
In a reprogrammable FPGA, each programmable switch is formed by a reprogrammable memory cell which is interconnected with a switching transistor which has its source and drain connected to the two circuit nodes. These circuit nodes are part of the integrated circuit which can be configured by a user of the FPGA. The configurable circuit has an array of logic elements and interconnections which are set by the state of a memory cell and hence its interconnected switching transistor. An example of such a reprogrammable switch is described in U.S. Pat. No. 5,633,518, entitled “Nonvolatile Reprogrammable Interconnect Cell With FN Tunneling and Programming Method Thereof,” and which issued May 27, 1997 to the present assignee.
A flash memory is a type of NVM (non-volatile memory). In a flash memory-based FPGA, the memory cell of each programmable switch is part of a homogeneous two-dimensional memory array by which electric charge on floating gates in the memory cells is programmed or erased. The floating gate of a memory cell is also shared with the corresponding switching transistor so that the transistor is turned on or off. Hence each switching transistor is connected by its source and drain is programmed to make (or break) a wiring interconnection, or to set the function or functions of a logic element.
The flash memory array is typically programmed by one initial erase step which erases all the memory cells of the array at once and then followed by a sequence of programming steps, which apply a data word to all columns in parallel and a selected row at a time. The whole array is usually programmed by one programming step per row.
As for all integrated circuits, the FPGA must be tested after being manufactured to determine whether the FPGA is operative or not. However, there are problems in testing an NVM-based (including a flash memory-based) FPGA. Since only a small percentage of the switching transistors are turned on in the FPGA for a user-configured circuit, the FPGA must be programmed several times into different test circuit configurations. Each test circuit configuration must be tested in order to achieve a good fault-coverage by using almost every switch in the configurable portion of the FPGA at least one time in one of these test circuit configurations. The total test time of a NVM-based FPGA is approximately the time required to erase and reprogram the FPGA a certain number of times until every switch is used once. Even in a flash memory-based FPGA in which a global erase is performed only once, it may take hours to test a part completely by using the standard programing method since one erase and programming cycle typically requires a few minutes. In comparison, the typical test time of other types of integrated circuits is a few seconds.
It should be evident that a test time of hours for one integrated circuit creates a serious problem. The manufacturer can either sell the NVM-based FPGA with either no or rudimentary testing and the hope that the integrated circuit is functional, or with full testing of the FPGA at a correspondingly high price. Neither alternative is acceptable.
On the other hand, the present invention is directed toward solving this testing problem and provides for the reduction of the total test time of an NVM-based FPGA and for the corresponding lowering of testing costs.
SUMMARY OF THE INVENTION
The present invention provides for a method of testing an FPGA having a plurality of programmable interconnects, or switches. Each programmable interconnect has an NVM memory cell interconnected with a switching transistor. Each NVM memory cell is arranged as part of a memory array of rows and columns. Each of the switching transistors is connected to the nodes of a plurality of logic elements and interconnections, which are organized into identical and/or differing tiles, the tiles organized into an array of rows and columns superimposed upon the memory array. The testing method has the steps of: selecting test circuit configurations by which identical tiles are identically programmed as much as possible; and simultaneously programming and simultaneously erasing pluralities of the memory rows corresponding to the tiles into the test circuit configurations. In this manner, the time for testing the FPGA is considerably reduced.
Additionally, the test circuit configurations programmed into the FPGA are tested at a lower supply voltage than that of normal operation. Programming of the memory cells (and hence the switching transistors) are performed at reduced programming and erasing pulse voltages and times by substantially ignoring retention and disturb effect margin amounts.
REFERENCES:
patent: 5498978 (1996-03-01), Takahashi et al.
patent: 5526312 (1996-06-01), Eltoukhy
patent: 5594363 (1997-01-01), Freeman et al.
patent: 5633518 (1997-05-01), Bronze
patent: 5744980 (1998-04-01), McGowan et al.
patent: 5867507 (1999-02-01), Beebe et al.
patent: 5920201 (1999-07-01), McHrotra et al.
patent: 6009259 (1999-12-01), Ikeda et al.
Hecht Volker
Saxe Timothy
Actel Corporation
Moise Emmanuel L.
Schafer Jonathan H.
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